Universitat Passau Veriication of Systolic Arrays in M2l(str)
نویسنده
چکیده
VLSI designs often show regular structures, where issues like temporal and spatial recursivity, and bidirectionality play a central role. This document introduces the modelling of a class of regular VLSI circuits, namely iterative systolic arrays, in a particular secondorder logic, and presents fully automatic veri cation of pipeline properties for an example from the literature.
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